This invention relates generally to the field of semiconductor devices, and more particularly to an improved dielectric layer liner for an integrated circuit.
Modem integrated circuits contain thousands of solid state electronic devices on a single chip. As the number of devices on a given chip increases, more levels of metallization are required to electrically couple the devices. The levels of metallization are built on top of each other and separated by a dielectric layer which prevents interference from one level to the next. Moreover, within a given metal level, the horizontal distance separating metallization lines must be reduced in order to minimize the chip size as device density increases. At the same time, metallization resistance and capacitance must be minimized in order to meet speed and performance requirements. Unfortunately, as the spacing decreases, the intralevel (on the same metal level) and interlevel (between metal levels) capacitances increase if a dielectric layer having the same dielectric constant is used.
Traditionally, the dielectric materials used to isolate metallization lines within the same level and between two different levels have had relatively high dielectric constants. For example, undoped and doped silicon dioxide layers such as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), and plasma and chemical vapor deposited tetraethylorthosilicate based (TEOS) oxides have been used as dielectric layers in multi-metallization structures. The semiconductor industry""s continuing demand for integrated circuits with ever increasing device densities and operating speeds requires dielectric materials having low dielectric constants in order to reduce capacitance between metallization lines and the speed degradation that results from this capacitance. However, although low dielectric constant materials typically provide reduced capacitance, many of these materials may also have shortcomings (such as an associated high leakage current) that need to be addressed.
According to the present invention, disadvantages and problems associated with previous integrated circuit structures have been substantially reduced or eliminated.
According to one embodiment of the present invention, an integrated circuit structure includes a plurality of solid state electronic devices and a plurality of conductive elements that electrically couple the electronic devices. The integrated circuit structure also includes a dielectric layer positioned between two or more of the conductive elements. A liner is positioned between at least a portion of the dielectric layer and a conductive element. The liner is formed from a compound that includes silicon and either carbon and nitrogen.
The present invention provides a number of important technical advantages. For example, the present invention provides a liner for use in conjunction with dielectric layers that reduces leakage current associated with certain low dielectric constant materials used for the dielectric layers. In one embodiment, this liner is made from silicon nitride; however, other appropriate materials may be used. Unlike previous dielectric layer liners, such as tetraethylosilicate (TEOS), the liner of the present invention reduces leakage current while also reducing the capacitance of the combined dielectric layer and liner. This capacitance is reduced even though the silicon nitride and other appropriate materials have a higher dielectric constant than TEOS and other previous liner materials. The reduction in capacitance is due, at least in part, to the relative thinness of the liner materials of the present invention. Other important technical advantages are readily apparent to those skilled in the art from the following figures, descriptions and claims.